PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 75

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed, if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
TABLE 6-2:
© 2006 Microchip Technology Inc.
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
PROGRAM_MEMORY
Name
Required
Sequence
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CFGS
Bit 6
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
—
—
—
—
bit 21
Bit 5
—
—
—
—
Advance Information
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INT0IE
FREE
EEIP
EEIF
EEIE
Bit 4
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
WRERR
RBIE
Bit 3
—
—
—
6.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 19.0 “Special Features of the
CPU” for more detail.
6.6
See Section 19.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TMR0IF
Flash Program Operation During
Code Protection
WREN
PIC18F1230/1330
LVDIP
LVDIE
LVDIF
Bit 2
PROTECTION AGAINST
SPURIOUS WRITES
INT0IF
Bit 1
WR
—
—
—
RBIF
Bit 0
RD
—
—
—
DS39758B-page 73
Values on
Reset
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