ADAU1966 AD [Analog Devices], ADAU1966 Datasheet - Page 19

• Manufacturer Part Number: ADAU1966
• Description: 16-Channel High Performance
• Manufacturer: AD [Analog Devices]

SERIAL CONTROL PORT: SPI CONTROL MODE
The ADAU1966 has an SPI control port that permits program-
ming and reading back of the internal control registers for the
DACs and clock system. A standalone mode is also available for
operation without serial control; it is configured at reset using the
SA_MODE pin. See the Standalone Mode section for details
about SA_MODE.
By default, the ADAU1966 is in I
SPI control mode by pulling CLATCH low three times. This
is done by performing three dummy writes to the SPI port (the
ADAU1966 does not acknowledge these three writes). Begin-
ning with the fourth SPI write, data can be written to or read
from the IC. The ADAU1966 can be taken out of SPI control
mode only by a full reset initiated by power cycling the IC.
The SPI control port of the ADAU1966 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
DACs. Figure 14 shows the format of the SPI signal. The first
byte is a global address with a read/write bit. For the ADAU1966,
the address is 0x06, shifted left one bit due to the R /W bit. The
second byte is the ADAU1966 register address, and the third
byte is the data.
POWER SUPPLY AND VOLTAGE REFERENCE
The ADAU1966 is designed for 3.3 V or 5 V analog and 2.5 V
digital supplies. To minimize noise pickup, the power supply
pins should be bypassed with 100 nF ceramic chip capacitors
placed as close to the pins as possible. A bulk aluminum
electrolytic capacitor of at least 22 μF should also be provided
for each rail on the same PC board as the codec. It is important
that the analog supply be as clean as possible.
The ADAU1966 includes a 2.5 V regulator driver that requires
only an external pass transistor and bypass capacitors to make a
2.5 V regulator from a 5 V or 3.3 V supply. The VSUPPLY and
VSENSE pins should be decoupled with no more than 10 μF, in
parallel with 100 nF high frequency bypassing. If the regulator
driver is not used, connect VSUPPLY and VDRIVE to GND
and leave VSENSE unconnected.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V or 5 V IOVDD supply and
are compatible with TTL and 3.3 V CMOS levels.
2
C mode, but it can be put into
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The temperature sensor internal voltage reference (V
is brought out on the TS_REF pin and should be bypassed as
close as possible to the chip with a parallel combination of
10 μF and 100 nF.
The internal band gap reference can be disabled in the
PLL_CLK_CTRL1 register by setting VREF_EN to 0; the CM
pin can be then be driven from an external source. This can be
used to scale the DAC output to the clipping level of a power
amplifier based on its power supply voltage.
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 10 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the
analog input and output signal pins. The output current should
be limited to less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The 16 DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The clock signals are all synchronous with the sample
rate. The normal stereo serial modes are shown in Figure 15.
The DAC serial data mode defaults to I
power-up and reset. The ports can also be programmed for left-
justified and right-justified (24-bit and 16-bit) operation using
DAC_CTRL0[7:6]. Stereo and TDM modes can be selected using
DAC_CTRL0[5:3]. The polarity of DBCLK and DLRCLK is
programmable according to the DAC_CTRL1[1] and DAC_
CTRL1[5] bits. The serial ports are programmable as the clock
masters according to the DAC_CTRL1[0] bit. By default, the
serial port is in slave mode.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The ADAU1966 serial ports also have several different TDM
serial data modes. The ADAU1966 can support a single data
line TDM16, a dual data line (TDM8), a quad data line
(TDM4), or eight data lines (TDM2). The DLRCLK can be
operated in both single-cycle pulse mode and a 50% duty
cycle mode. Both 16 DBCLKs or 32 DBCLKs per channel are
selectable for each mode.
The I/O pins of the serial ports are defined according to the
serial mode that is selected. For a detailed description of the
function of each pin in TDM and stereo modes, see Table 23.
2
S (1 BCLK delay) upon
ADAU1966
TS_REF
)