ADAU1966 AD [Analog Devices], ADAU1966 Datasheet - Page 22

• Manufacturer Part Number: ADAU1966
• Description: 16-Channel High Performance
• Manufacturer: AD [Analog Devices]

ADAU1966
ADDITIONAL MODES
The ADAU1966 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit DBCLK. See
Figure 17 for an example of a DAC TDM data transmission mode
that does not require a high speed DBCLK or an external
MCLK. This configuration is applicable when the ADAU1966
master clock is generated by the PLL with the DLRCLK as the
PLL reference frequency.
TDM-DSDATAx
DSDATAx
DLRCLK
INTERNAL
INTERNAL
DBCLK
DSDATAx
DLRCLK
DLRCLK
DBCLK
DBCLK
MSB
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission)
Figure 17. Serial DAC Data Transmission in TDM Format Without DBCLK
32 BITS
Figure 18. Inverted DBCLK Mode in DAC Serial Data Transmission
DATA MUST BE VALID
AT THIS BCLK EDGE
(Applicable Only If PLL Locks to DLRCLK)
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To relax the requirement for the setup time of the ADAU1966
in cases of high speed TDM data transmission, the ADAU1966
can latch in the data using the falling edge of DBCLK; see the
BCLK_EDGE bit in the DAC_CTRL1 register. This effectively
dedicates the entire BCLK period to the setup time. This mode
is useful in cases where the source has a large delay time in the
serial data driver. Figure 18 shows this inverted DBCLK mode
of data transmission.