ADAU1966 AD [Analog Devices], ADAU1966 Datasheet - Page 17

• Manufacturer Part Number: ADAU1966
• Description: 16-Channel High Performance
• Manufacturer: AD [Analog Devices]

Table 14. MCS and f
Sample Rate Select (FS)
DAC_CTRL0[2:1]
32 kHz, b00
44.1 kHz, b00
48 kHz, b00
64 kHz, b01
88.2 kHz, b01
96 kHz, b01
128 kHz, b10 or b11
176.4 kHz, b10 or b11
192 kHz, b10 or b11
STANDALONE MODE
The ADAU1966 can operate without a typical I
connection to a microcontroller. This standalone mode is
made available by setting the SA_MODE (Pin 46) to high
(IOVDD). All registers are set to default except the options
shown in Table 15.
Table 15. SA_MODE Settings
Pin No.
42
43
44
45
When both SA_MODE and Pin 45 are set high, TDM mode is
selected. Table 16 shows the available TDM modes; these modes
are set by connecting Pin 31 (DSDATA8) and Pin 32 (DSDATA7)
to GND or IOVDD.
Table 16. TDM Modes
Pin No.
32:31
When the ADAU1966 is powered up in SA_MODE and the
PU/ RST pin is asserted high, the MCLKO pin provides a buff-
ered version of the MCLKI pin, whether the source is a crystal
or an active oscillator.
I
The ADAU1966 has an I
mits programming and reading back of the internal control
registers for the DACs and clock system. The I
ADAU1966 is a 2-wire interface consisting of a clock line, SCL,
2
C CONTROL PORT
Setting
0
1
0
1
0
1
0
1
Setting
00
01
10
11
Function
Master mode serial audio interface (SAI)
Slave mode SAI
MCLK = 256 × f
MCLK = 384 × f
AVDD = 5.0 V (CM = 2.25 V)
AVDD = 3.3 V (CM = 1.50 V)
I
TDM modes, determined by Pin 31 and Pin 32
S
2
S SAI format
Modes
2
C-compatible control port that per-
Function
TDM4—DLRCLK pulse
TDM8—DLRCLK pulse
TDM16—DLRCLK pulse
TDM8—DLRCLK 50% duty cycle
Ratio
256 × f
256 × f
256 × f
128 × f
128 × f
128 × f
64 × f
64 × f
64 × f
S
S
, PLL on
, PLL on
S
S
S
S
S
S
S
S
S
Setting 0, b00
2
C interface of the
2
C or SPI
MCLK (MHz)
8.192
11.2896
12.288
8.192
11.2896
12.288
8.192
11.2896
12.288
Rev. 0 | Page 17 of 52
Master Clock Select (MCS), PLL_CLK_CTRL0[2:1]
Ratio
384 × f
384 × f
384 × f
192 × f
192 × f
192 × f
96 × f
96 × f
96 × f
Setting 1, b01
S
S
S
S
S
S
S
S
S
and a data line, SDA. SDA is bidirectional, and the ADAU1966
drives SDA either to acknowledge the master (ACK) or to send
data during a read operation. The SDA pin for the I
open-drain collector and requires a 2 kΩ pull-up resistor. A write
or read access occurs when the SDA line is pulled low while the
SCL line is high, indicated by a start in Figure 12 and Figure 13.
SDA is only allowed to change when SCL is low except when a
start or stop condition occurs, as shown in Figure 12 and Figure 13.
The first eight bits of the data-word consist of the device address
and the R/W bit. The device address consists of an internal built-in
address (0x04) and two address pins, ADDR1 and ADDR0. The
two address bits allow four ADAU1966 devices to be used in a
system. Initiating a write operation to the ADAU1966 involves
sending a start condition and then sending the device address
with the R /W bit set low. The ADAU1966 responds by issuing
an acknowledge to indicate that it has been addressed. The user
then sends a second frame telling the ADAU1966 which register
is required to be written. Another acknowledge is issued by the
ADAU1966. Finally, the user can send another frame with the
eight data bits required to be written to the register. A third
acknowledge is issued by the ADAU1966 after which the user
can send a stop condition to complete the data transfer.
A read operation requires that the user first write to the
ADAU1966 to point to the correct register and then read the
data. This is achieved by sending a start condition followed by
the device address frame, with the R /W bit low, and then the
register address frame. Following the acknowledge from the
ADAU1966, the user must issue a repeated start condition. The
next frame is the device address with the R /W bit set high. On
the next frame, the ADAU1966 outputs the register data on the
SDA line. A stop condition completes the read operation.
Table 17. I
ADDR1
0
0
1
1
MCLK
12.288
16.9344
18.432
12.288
16.9344
18.432
12.288
16.9344
18.432
2
C Addresses
Ratio
512 × f
512 × f
512 × f
256 × f
256 × f
256 × f
128 × f
128 × f
128 × f
ADDR0
0
1
0
1
Setting 2, b10
S
S
S
S
S
S
S
S
S
MCLK
16.384
22.5792
24.576
16.384
22.5792
24.576
16.384
22.5792
24.576
Slave Address
0x04
0x24
0x44
0x64
Ratio
768 × f
768 × f
768 × f
384 × f
384 × f
384 × f
192 × f
192 × f
192 × f
Setting 3, b11
ADAU1966
S
S
S
S
S
S
S
S
S
2
C port is an
MCLK
24.576
33.8688
36.864
24.576
33.8688
36.864
24.576
33.8688
36.864