ADAU1966 AD [Analog Devices], ADAU1966 Datasheet - Page 31

• Manufacturer Part Number: ADAU1966
• Description: 16-Channel High Performance
• Manufacturer: AD [Analog Devices]

DAC CONTROL 1 REGISTER
Address: 0x07, Reset: 0x00, Name: DAC_CTRL1
Table 32. Bit Descriptions for DAC_CTRL1
Bits
7
6
5
4
2
1
0
Bit Name
BCLK_GEN
LRCLK_MODE
LRCLK_POL
SAI_MSB
BCLK_RATE
BCLK_EDGE
SAI_MS
Settings
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
DBCLK Generation. When the PLL is locked to DLRCLK, it is possible to run
the ADAU1966 without an external DBCLK.
Normal Operation—DBCLK
Internal DBCLK Generation
DLRCLK Mode Select. Only Valid for TDM modes.
50% Duty Cycle DLRCLK
Pulse Mode
DLRCLK Polarity. Allows the swapping of data between channels.
Left/Odd channels are DLRCLK Low (Normal)
Left/Odd channels are DLRCLK High (Inverted)
MSB Position.
MSB First DSDATA
LSB First DSDATA
DBCLK Rate. Number of DBCLK cycles per DLRCLK Frame. Used only for
generating DBCLK in Master Mode operation (SAI_MS = 1).
32 Cycles per Frame
16 Cycles per Frame
DBCLK Active Edge. Adjust the polarity of the DBCLK leading edge.
Latch in Rising Edge
Latch in Falling Edge
Serial Interface Master. Both DLRCLK and DBCLK become master when
enabled.
DLRCLK/DBCLK Slave
DLRCLK/DBCLK Master
Rev. 0 | Page 31 of 52
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
ADAU1966
Access
RW
RW
RW
RW
RW
RW
RW