ADAU1966 AD [Analog Devices], ADAU1966 Datasheet - Page 24

• Manufacturer Part Number: ADAU1966
• Description: 16-Channel High Performance
• Manufacturer: AD [Analog Devices]

ADAU1966
REGISTER DETAILS
PLL AND CLOCK CONTROL 0 REGISTER
Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0
Table 25. Bit Descriptions for PLL_CLK_CTRL0
Bits
[7:6]
[5:4]
3
[2:1]
0
Bit Name
PLLIN
XTAL_SET
SOFT_RST
MCS
PUP
Settings
00
01
10
11
00
01
10
11
00
01
10
11
0
1
0
1
Description
PLL Input Select. Selects between MCLKI/XTALI or DLRCLK as the input to
the PLL.
MCLKI or XTALI
DLRCLK
Reserved
Reserved
XTAL Oscillator Setting. XTALO pin status.
XTAL Oscillator Enabled
Reserved
Reserved
XTALO Off
Software Reset Control. This bit resets all circuitry inside the IC, except
I
except 0x00 and 0x01. The PLL_CLK_CTRLx registers do not change state.
Normal Operation
Device in Reset
Master Clock Select. MCLKI/XTALI pin functionality (PLL active), master
clock rate setting. The following values are for the f
kHz to 48 kHz. See Table 14 for details when using other f
256 × f
384 × f
512 × f
768 × f
Master Power-Up Control. This bit must be set to 1 as the first register
write to power up the IC.
Master Power-Down
Master Power-Up
2
C/SPI communications. All control registers are reset to default values,
S
S
S
S
MCLK (44.1 kHz or 48 kHz)
MCLK (44.1 kHz or 48 kHz)
MCLK (44.1 kHz or 48 kHz)
MCLK (44.1 kHz or 48 kHz)
Rev. 0 | Page 24 of 52
S
rate window from 32
S
selections.
Reset
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW