ADAU1966 AD [Analog Devices], ADAU1966 Datasheet - Page 15

• Manufacturer Part Number: ADAU1966
• Description: 16-Channel High Performance
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS (DACS)
The 16 ADAU1966 digital-to-analog converter (DAC) channels
are differential for improved noise and distortion performance
and are voltage output for simplified connection. The DACs
include on-chip digital interpolation filters with 68 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 256× (48 kHz range), 128× (96 kHz range), or
64× (192 kHz range). Each channel has its own independently
programmable attenuator, adjustable in 255 steps in increments
of 0.375 dB. Digital inputs are supplied through eight serial data
input pins (two channels on each pin), a common frame clock
(DLRCLK), and a bit clock (DBCLK). Alternatively, any one of the
TDM modes can be used to access up to 16 channels on a single
TDM data line.
The ADAU1966 has a low propagation delay mode; this mode
is an option for an f
CTRL0[2:1]. By setting these bits to b11, the propagation delay
is reduced by the amount shown in Table 8. The shorter delay is
achieved by reducing the amount of digital filtering; the nega-
tive impact of selecting this mode is reduced audio frequency
response and increased out-of-band energy.
When AVDD is supplied with 5 V, each analog output pin has a
nominal common-mode (CM) dc level of 2.25 V and swings
±8.49 V p-p (3 V rms differential) from a 0 dBFS digital input
signal. An AVDD of 3.3 V generates a CM dc voltage of 1.5 V
and allows differential audio swings of ±5.66 V p-p (2 V rms)
from a 0 dBFS digital input signal. The differential analog
outputs require only a single-order passive differential RC filter
to provide the specified DNR performance; see Figure 9 for an
example filter. The outputs can easily drive differential inputs
on a separate PCB through cabling as well as differential inputs
on the same PCB.
If more signal level is required or if a more robust filter is needed, a
single op amp gain stage designed as a second-order, low-pass
Bessel filter can be used to remove the high frequency out-of-
band noise present on each pin of the differential outputs. The
choice of components and design of this circuit is critical to
yield the full DNR of the DACs (see the recommended passive
and active circuits in Figure 9 and Figure 10). This filter can be
built into an active difference amplifier to provide a single-ended
output with gain, if necessary. Note that the use of op amps with
low slew rate or low bandwidth can cause high frequency noise
and tones to fold down into the audio band; exercise care when
selecting these components.
Table 13. DAC Power vs. Performance
Register Setting
Total AVDD Current
SNR
THD + N (−1 dbFS signal)
S
of 192 kHz and is enabled in Register DAC_
Best Performance
82 mA
Reference
Reference
Rev. 0 | Page 15 of 52
Good Performance
73 mA
−0.2 dB
−1.8 dB
The ADAU1966 offers control over the analog performance
of the DACs; it is possible to program the registers to reduce
the power consumption with the trade-off of lower SNR and
THD + N. The reduced power consumption is the result of
changing the internal bias current to the analog output
amplifiers.
Register DAC_POWER1 to Register DAC_POWER4 present
four basic settings for the DAC power vs. performance in each
of the 16 channels: best performance, good performance, low
power, and lowest power. Alternatively, in Register PLL_CLK_
CTRL1[7:6], the LOPWR_MODE bits offer global control over
the power and performance for all 16 channels. The default
setting is b00. This setting allows the channels to be controlled
individually using the DAC_POWERx registers. Setting b10
and Setting b11 select the low power and lowest power settings.
The data presented in Table 13 shows the result of setting all
16 channels to each of the four settings. The SNR and THD + N
specifications are shown in relation to the measured perfor-
mance of a device at the best performance setting.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
Upon powering the ADAU1966 and asserting the PU/ RST pin
high, the part starts in either standalone mode (SA_MODE) or
program mode, depending on the state of SA_MODE (Pin 46).
The clock functionality of SA_MODE is described in the
Standalone Mode
ADAU1966 is for the MCLKO pin to feed a buffered output of
the MCLKI signal. The default for the DLRCLK and DBCLK
ports is slave mode; the DAC must be driven with a coherent set
of MCLK, LRCLK, and BCLK signals to function.
The MCLKO pin can be programmed to provide different clock
signals using Register Bits PLL_CLK_CTRL1[5:4]. The default,
b10, provides a buffered copy of the clock signal that is driving
the MCLKI pin. Two modes, b00 and b01, provide low jitter
clock signals. The b00 setting yields a clock rate between 4 MHz
and 6 MHz, and b01 yields a clock rate between 8 MHz and
12 MHz. Both of these clock frequencies are scaled as ratios of
MCLK automatically inside the ADAU1966. As an example, an
MCLK of 8.192 MHz and a setting of b00 yield an MCLKO of
(8.192/2) = 4.096 MHz. Alternatively, an MCLK of 36.864 MHz
and a setting of b01 yield an MCLKO frequency of (36.864/3) =
12.288 MHz. The setting b11 shuts off the MCLKO pin.
section. In program mode, the default for the
Low Power
64 mA
−1.5 dB
−3.0 dB
Lowest Power
54 mA
−14.2 dB
−5.8 dB
ADAU1966