ADAU1966 AD [Analog Devices], ADAU1966 Datasheet - Page 16

• Manufacturer Part Number: ADAU1966
• Description: 16-Channel High Performance
• Manufacturer: AD [Analog Devices]

ADAU1966
After the PU/ RST pin has been asserted high, the PLL_CLK_
CTRLx registers (0x00 and 0x01) can be programmed. The
on-chip phase-locked loop (PLL) can be selected to use the
clock appearing at the MCLKI/XTALI pin at a frequency of
256, 384, 512, or 768 times the sample rate (f
the 48 kHz mode from the master clock select (MCS) setting,
as described in
quency stays at the same absolute frequency; therefore, the
actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if
the ADAU1966 is programmed in 256 × f
of the master clock input is 256 × 48 kHz = 12.288 MHz. If the
ADAU1966 is then switched to 96 kHz operation (by writing to
DAC_CTRL0 [2:1]), the frequency of the master clock should
remain at 12.288 MHz, which is 128 × f
192 kHz mode, MCS becomes 64 × f
The internal clock for the digital core varies by mode: 512 × f
(48 kHz mode), 256 × f
mode). By default, the on-board PLL generates this internal
master clock from an external clock.
The PLL should be powered and stable before the ADAU1966 is
used as a source for quality audio. The PLL is enabled by reset
and does not require writing to the I
operation.
With the PLL enabled, the performance of the ADAU1966 is
not affected by jitter as high as a 300 ps rms time interval error
(TIE). If the internal PLL is not used, it is best to use an independ-
ent crystal oscillator to generate the master clock.
If the ADAU1966 is to be used in direct MCLK mode, the PLL
can be powered down in the PDN_THRMSENS_CTRL_1 regis-
ter. For direct MCLK mode, a 512 × f
mode) master clock must be used as MCLK, and the CLK_SEL
bit in the PLL_CLK_CTRL1 register must be set to b1.
The ADAU1966 PLL can also be programmed to run from an
external LRCLK. When the PLLIN bits in the PLL_CLK_CTRL0
register are set to 01 and the appropriate loop filter is connected
to the LF pin (see Figure 8), the ADAU1966 PLL generates all
of the necessary internal clocks for operation with no external
MCLK. This mode reduces the number of high frequency
signals in the design, reducing EMI emissions.
It is possible to further reduce EMI emissions of the circuit by
using the internal DBCLK generation setting of the BCLK_GEN
Table 14
S
. In 96 kHz mode, the master clock fre-
(96 kHz mode), or 128 × f
S
2
.
C or SPI port for normal
S
S
(referenced to 48 kHz
in this example. In
S
mode, the frequency
S
), referenced to
S
(192 kHz
S
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bit in the DAC_CTRL1 register. With the BCLK_GEN bit set to
b1 (internal) and the SAI_MS bit set to b0 (slave), the ADAU1966
generate its own DBCLK; this works with the PLL input set to
either MCLKI/XTALI or DLRCLK. DLRCLK is the only required
clock in DLRCLK PLL mode.
POWER-UP AND RST
Power sequencing for the ADAU1966 should start with AVDD
and IOVDD, followed by DVDD. It is very important that
AVDD be settled at a regulated voltage and that IOVDD be
within 10% of regulated voltage before applying DVDD. When
using the ADAU1966 internal regulator, this timing occurs by
default.
To guarantee proper startup, the PU/ RST pin should be pulled
low by an external resistor and then driven high after the power
supplies have stabilized. The PU/ RST can also be pulled high
using a simple RC network.
Driving the PU/ RST pin low puts the part into a very low power
state (<3 μA). All functionality of the ADAU1966 is disabled
until the PU/ RST pin is asserted high. Once this pin is asserted
high, the ADAU1966 requires 300 ms to stabilize. The MMUTE
bit in the DAC_CTRL0 register must be toggled for operation.
The PUP bit in the PLL_CLK_CTRL0 register can be used to
power down the ADAU1966. Engaging the master power-down
puts the ADAU1966 in an idle state while maintaining the set-
tings of all registers. Additionally, the power-down bits in the
PDN_THRMSENS_CTRL1 register (TS_PDN, PLL_PDN, and
VREG_PDN) can be used to power down individual sections of
the ADAU1966.
The SOFT_RST bit in the PLL_CLK_CTRL0 register sets all of
the control registers to their default settings while maintaining
the internal clocks in default mode. The SOFT_RST bit does
not power down the analog outputs; toggling this bit does not
cause audible popping sounds at the differential analog outputs.
Proper startup of the ADAU1966 should proceed as follows:
1.
2.
3.
4.
5.
Apply power to the ADAU1966 as described previously.
Assert the PU/ RST pin high after power supplies have
stabilized.
Set the PUP bit to b1.
Program all necessary registers for the desired settings.
Set the MMUTE bit to b0 to unmute all channels.