FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 10

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

SMSC DS – FDC37N769
TQFP
TQFP
PIN #
81,91
80,90
78,88
83,85
82,84
PIN #
71
nData
Terminal
Ready
nClear to
Send
nData Set
Ready
nData
Carrier
Detect
nRing
Indicator
nPrinter
Select
Input/FDC
nStep
Pulse
(Note
NAME
NAME
3
)
nDTR1
nDTR2
nCTS1
nCTS2
nDSR1
nDSR2
nDCD1
nDCD2
nRI1
nRI2
nSLCTIN
nSTEP
SYMBOL
SYMBOL
PARALLEL PORT INTERFACE (NOTE 2)
DATASHEET
(OD14/OP1
BUFFER
BUFFER
4)/OD12
(Note
TYPE
TYPE
O6
I
I
I
I
1
)
Page 10 of 137
Active low Data Terminal Ready outputs for the serial
port. Handshake output signal notifies modem that
the UART is ready to establish data communication
link. This signal can be programmed by writing to bit 0
of Modem Control Register (MCR). The hardware
reset will reset the nDTR signal to inactive mode
(high).
operation.
Active low Clear to Send inputs for the serial port.
Handshake signal which notifies the UART that the
modem is ready to receive data.
monitor the status of nCTS signal by reading bit 4 of
Modem Status Register (MSR). A nCTS signal state
change from low to high after the last MSR read will
set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable
Register is set, the interrupt is generated when nCTS
changes state. The nCTS signal has no effect on the
transmitter. Note: Bit 4 of MSR is the complement of
nCTS.
Active low Data Set Ready inputs for the serial port.
Handshake signal which notifies the UART that the
modem is ready to establish the communication link.
The CPU can monitor the status of nDSR signal by
reading bit 5 of Modem Status Register (MSR). A
nDSR signal state change from low to high after the
last MSR read will set MSR bit 1 to a 1. If bit 3 of
Interrupt Enable Register is set, the interrupt is
generated when nDSR changes state. Note: Bit 5 of
MSR is the complement of nDSR.
Active low Data Carrier Detect inputs for the serial
port. Handshake signal which notifies the UART that
carrier signal is detected by the modem. The CPU
can monitor the status of nDCD signal by reading bit 7
of Modem Status Register (MSR). A nDCD signal
state change from low to high after the last MSR read
will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated when nDCD
changes state.
complement of nDCD.
Active low Ring Indicator inputs for the serial port.
Handshake signal which notifies the UART that the
telephone ring signal is detected by the modem. The
CPU can monitor the status of nRI signal by reading
bit 6 of Modem Status Register (MSR). A nRI signal
state change from low to high after the last MSR read
will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated when nRI
changes state.
complement of nRI.
This active low output selects the printer. This is the
complement of bit 3 of the Printer Control Register.
Refer to Parallel Port description for use of this pin in
ECP and EPP mode.
See FDC Pin definition.
nDTR is forced inactive during loop mode
DESCRIPTION
DESCRIPTION
Note:
Note:
Bit 7 of MSR is the
Bit 6 of MSR is the
The CPU can
Rev. 02-16-07