FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 83

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

Register Definitions
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are
supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict
with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that
mode. The port registers vary depending on the mode field in the ecr (Table 68). Table 67 lists these dependencies.
Operation of the devices in modes other that those specified is undefined.
Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers.
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
DATA and ecpAFifo PORT
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising edge of the
nIOW input.
During a READ operation, PD0 - PD7 ports are read and output to the host CPU.
SMSC DS – FDC37N769
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
NInit
NSelectIn
NAME
NAME
The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
MODE
000
001
010
011
100
101
110
111
ADDRESS (Note 1)
TYPE
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the configuration registers)
(Reserved)
Test mode
Configuration mode
O
O
+000h R/W
+000h R/W
+001h R/W
+002h R/W
+400h R/W
+400h R/W
+400h R/W
+401h R/W
+402h R/W
+400h R
Sets the transfer direction (asserted = reverse, deasserted = forward). This
pin is driven low to place the channel in the reverse direction. The
peripheral is only allowed to drive the bi-directional data bus while in ECP
Mode and HostAck is low and nSelectIn is high.
Always deasserted in ECP mode.
Table 67 - ECP Register Definitions
DATASHEET
Table 68 - Mode Descriptions
(Refer to ECR Register Description)
Page 83 of 137
DESCRIPTION
ECP MODES
000-001
011
010
011
110
111
111
All
All
All
DESCRIPTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
FUNCTION
Rev. 02-16-07