FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 21

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

MOTOR ENABLE 3, Bit 7
The MOTOR ENABLE 3 bit controls the MTR3 disk interface output. A logic “1” in this bit causes the output to go
active.
Drive Select Encoding
The FDC37N769 can support two types of drive select encoding: Internal 2 Drive decoding (Table 11) and External 2-
to-4 Drive decoding (Table 13). Internal 2 Drive decoding specifies support for a maximum of two floppy drives.
External 2-to-4 Drive decoding expands support for four floppy drives but requires an external 2-to-4 decoder. The
drive select encoding is determined by the EXTx4 bit in CR05.
The FDC37N769 can also internally swap drive 0 and drive 1 using the Swap Drv 0, 1 bit in CR05. Table 12
illustrates Internal 2-Drive decoding with drive 0 and drive 1 swapped. Table 14 illustrates External 2-to-4 Drive
decoding with drive 0 and drive 1 swapped.
SMSC DS – FDC37N769
Bit 7
Bit 7
X
X
X
1
0
X
X
X
1
0
DIGITAL OUTPUT REGISTER
Bit 7
DIGITAL OUTPUT REGISTER
X
X
X
X
X
X
1
0
Bit 6
Bit 6
X
X
X
1
0
X
X
X
1
0
Bit 5
Bit 5
Bit 6
X
X
X
1
0
X
X
X
X
X
1
0
X
X
1
X
X
0
Table 13 - External 2-to-4 Drive Decode: Drives 0 and 1 Not Swapped
DIGITAL OUTPUT REGISTER
Table 11 - Internal 2 Drive Decode: Drives 0 and 1 Not Swapped
Bit 4
Bit 4
Table 12 - Internal 2-Drive Decode: Drive 0 and 1 Swapped
X
X
X
1
0
X
X
X
1
0
Bit 5
X
1
X
X
X
0
X
X
Bit1
Bit1
X
0
0
1
1
X
0
0
1
1
Bit 0
Table 10 - Drive Activation Values
Bit 4
Bit 0
X
DRIVE
0
1
2
3
0
1
0
1
X
X
X
X
X
X
1
0
DATASHEET
X
0
1
0
1
OUTPUTS (ACTIVE LOW)
DRIVE SELECT OUTPUTS
Bit1
DRIVE SELECT
Page 21 of 137
0
0
1
1
0
0
1
1
(ACTIVE LOW)
nDS1
DOR VALUE
1CH
2DH
4EH
8FH
nDS1
0
1
1
1
1
Bit 0
1
0
1
1
1
0
1
0
1
0
1
0
1
nDS0
nDS0
1
0
1
1
1
DRIVE SELECT
0
1
1
1
1
nDS1
(ACTIVE LOW)
0
0
1
1
0
0
1
1
OUTPUTS
nDS0
MOTOR ON OUTPUTS
MOTOR ON OUTPUTS
0
1
0
1
0
1
0
1
(ACTIVE LOW)
(ACTIVE LOW)
nMTR1
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nMTR1
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nMTR1
(ACTIVE LOW)
MOTOR ON
1
1
1
1
1
1
1
1
OUTPUTS
nMTR0
nMTR0
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nBIT 5
nMTR0
nBIT 4
nBIT 4
nBIT 4
nBIT 4
nBIT 4
0
0
0
0
1
1
1
1
Rev. 02-16-07