FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 20

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

nDRIVE SELECT 0, Bit 5
Active low status of the DS0 disk interface output.
nDRIVE SELECT 1, Bit 6
Active low status of the DS1 disk interface output.
nDRV2, Bit 7
Active low status of the DRV2 disk interface input.
DIGITAL OUTPUT REGISTER (DOR)
The Digital Output register (Base Address + 2) controls the drive select and motor enables of the disk interface
outputs (Table 9 and Table 10). The DOR also contains the DMA logic enable and a software reset bit. The DOR is
read/write and unaffected by a software reset.
DOR Bit Descriptions
DRIVE SELECT, Bits 0 - 1
These two bits are binary encoded for the four drive selects DS0-DS3, thereby allowing only one drive to be selected
at one time.
nRESET, Bit 2
A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR
register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this
register is a valid method of issuing a software reset.
DMAEN, Bit 3
PC/AT and Model 30 Interface Mode
In PC/AT and Model 30 mode writing this bit to logic “1” will enable the DRQ, nDACK, TC and FINTR outputs. This
bit being a logic “0” will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance
state. In PC/AT and Model 30 mode the DMAEN bit is a logic “0” after a reset.
PS/2 Interface Mode
In PS/2 mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset the DRQ, nDACK, TC, and
FINTR pins will remain enabled, but the DMAEN bit will be cleared to a logic “0”.
MOTOR ENABLE 0, Bit 4
This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active.
MOTOR ENABLE 1, Bit 5
This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active.
MOTOR ENABLE 2, Bit 6
The MOTOR ENABLE 2 bit controls the MTR2 disk interface output. A logic “1” in this bit will cause the output pin to
go active.
SMSC DS – FDC37N769
CONDITION
RESET
MOT EN3 MOT EN2 MOT EN1 MOT EN0 DMAEN
7
0
6
0
Table 9 - Digital Output Register
DATASHEET
5
0
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4
0
3
0
nRESET
2
0
DRIVE
SEL1
1
0
DRIVE
SEL0
0
0
Rev. 02-16-07