FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 68

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

The Affects of RESET on the UART Registers
The RESET Function (Table 57) details the affects of RESET on each of the Serial Port registers.
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR interrupts occur as
follows:
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts occur as follows:
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur
as follows:
SMSC DS – FDC37N769
1.
2.
3.
4.
1.
2.
3.
4.
5.
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
Line Control Reg.
MODEM Control Reg.
Line Status Reg.
MODEM Status Reg.
TXD1, TXD2
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
OUT2B
RTSB
DTRB
OUT1B
RCVR FIFO
XMIT FIFO
The receive data available interrupt will be issued when the FIFO has reached its programmed trigger
level; it is cleared as soon as the FIFO drops below its programmed trigger level.
The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is
cleared when the FIFO drops below the trigger level.
The receiver line status interrupt (IIR=06H), has higher priority than the received data available
(IIR=04H) interrupt.
The data ready bit (LSR bit 0)is set as soon as a character is transferred from the shift register to the
RCVR FIFO. It is reset when the FIFO is empty.
A FIFO time-out interrupt occurs if all the following conditions exist:
This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a
12 bit character.
Character times are calculated by using the RCLK input for a clock signal (this makes the delay
proportional to the baud rate).
When a time-out interrupt has occurred it is cleared and the timer reset when the CPU reads one
character from the RCVR FIFO.
When a time-out interrupt has not occurred the time-out timer is reset after a new character is received
or after the CPU reads the RCVR FIFO.
REGISTER/SIGNAL
at least one character is in the FIFO
The most recent serial character received was longer than 4 continuous character times ago. (If 2
stop bits are programmed, the second one is included in this time delay.)
The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
DATASHEET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET/Read LSR
RESET/Read RBR
RESET/ReadIIR/Write THR
RESET
RESET
RESET
RESET
RESET/FCR1*FCR0/_FCR0
RESET/FCR1*FCR0/_FCR0
Table 57 - RESET Function
RESET CONTROL
Page 68 of 137
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5 - 6 high
Bits 0 - 3 low; Bits 4 - 7 input
High
Low
Low
Low
High
High
High
High
All bits low
All bits low
RESET STATE
Rev. 02-16-07