FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet - Page 98

• Manufacturer Part Number: FDC37N769_07
• Description: 3.3V Super I/O Controller with Infrared Support for Portable Applications
• Manufacturer: SMSC [SMSC Corporation]

CR00
CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. The default
value of this register after power up is 28H (Table 76).
NOTE
CR01
CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. The default
value of this register after power up is 9CH (Table 77).
NOTE
SMSC DS – FDC37N769
BIT NO.
BIT NO.
0,1
5,6
4,5,6
1
1
DEFAULT INDEX
2
3
4
7
0:2
: Power Down bits disable the respective logical device and associated pins, however the power down bit
3
7
does not disable the selected address range for the logical device. To disable the host address registers the
logical device’s base address must be set below 100h. Devices that are powered down but still reside at a
valid I/O base address will participate in Plug-and-Play range checking.
Power Down bits disable the respective logical device and associated pins, however the power down bit
does not disable the selected address range for the logical device. To disable the host address registers the
logical device’s base address must be set below 100h. Devices that are powered down but still reside at a
valid I/O base address will participate in Plug-and-Play range checking.
00H
03H
00H
00H
Reserved
Parallel Port Power
Parallel Port Mode
Reserved
Reserved
Lock CRx
Reserved
FDC Power
Reserved
Valid
CR2C
CR2D
CR2E
CR2F
BIT NAME
BIT NAME
1
DB7
1
Read Only. A read returns “0”.
A high level on this bit, supplies power to the Parallel Port (Default). A low level on
this bit puts the Parallel Port in low power mode.
Parallel Port Mode. A high level on this bit, sets the Parallel Port for Printer Mode
(Default). A low level on this bit enables the Extended Parallel port modes. Refer
to Bits 0 and 1 of CR4
Read Only. A read returns “1”.
Read Only. A read returns “0”.
A high level on this bit enables the reading and writing of CR00 -CR2F (Default).
A low level on this bit disables the reading and writing of CR00 - CR2F. Note:
once the Lock Crx bit is set to “0”, this bit can only be set to “1” by a hard reset or
power-up reset.
Read Only. A read returns 0
A high level on this bit, supplies power to the FDC (default). A low level on this
bit puts the FDC in low power mode.
Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0.
A high level on this software controlled bit can be used to indicate that a valid
configuration cycle has occurred. The control software must take care to set
this bit at the appropriate times. Set to zero after power up. This bit has no
effect on any other hardware in the chip.
DB6
Reserved
DATASHEET
DB5
Table 76 - CR00
Table 77 - CR01
Page 98 of 137
IR Half Duplex Turnaround Time
DB4
Software Select A
Software Select B
DB3
DESCRIPTION
DESCRIPTION
Serial Port 2 DMA Channel Select
DB2
DB1
DB0
Rev. 02-16-07