MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 115

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

8.4.2.1 Power-On Reset
MC68HC908AB32
MOTOROLA
—
Rev. 1.0
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
CGMXCLK
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Freescale Semiconductor, Inc.
IRST
RST
IAB
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A POR pulse is generated
The internal reset signal is asserted
The SIM enables CGMOUT
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow the oscillator to stabilize
System Integration Module (SIM)
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ILLEGAL ADDRESS RST
Figure 8-6. Sources of Internal Reset
ILLEGAL OPCODE RST
RST PULLED LOW BY MCU
Figure 8-5. Internal reset timing
COPRST
32 CYCLES
POR
LVI
INTERNAL RESET
System Integration Module (SIM)
32 CYCLES
Reset and System Initialization
VECTOR HIGH
Technical Data
115