MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 148

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

Clock Generator Module (CGM)
9.6.3 PLL Programming Register (PPG)
Technical Data
148
Address:
Bits [3:0] — Reserved for test
The PLL programming register contains the programming information
for the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
MUL[7:4] — Multiplier Select Bits
Reset:
Read:
Write:
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as 0.
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write zeros to Bits [3:0] whenever writing to PBWC.
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See
9.4.2.4 Programming the
bits configures the modulo feedback divider the same as a value of
$1. Reset initializes these bits to $6 to give a default multiply value
of 6.
Freescale Semiconductor, Inc.
For More Information On This Product,
$001E
MUL7
Bit 7
0
Figure 9-8. PLL Programming Register (PPG)
Clock Generator Module (CGM)
Go to: www.freescale.com
MUL6
6
1
MUL5
5
1
PLL). A value of $0 in the multiplier select
MUL4
4
0
VRS7
9.4.2.1 PLL Circuits
3
0
MC68HC908AB32
VRS6
2
1
VRS5
1
1
MOTOROLA
—
and
Rev. 1.0
VRS4
Bit 0
0