MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 325

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

17.6.3 Port D Input Pullup Enable Register (PTDPUE)
MC68HC908AB32
MOTOROLA
—
Rev. 1.0
Address:
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 17-5
The port D input pullup enable register (PTDPUE) controls the input
pullup device for each of the eight port D pins. Each bit is individually
configurable and requires that the data direction register, DDRD, bit be
configured as an input. Each pullup is automatically and dynamically
disabled when a port bit’s DDRD is configured for output mode.
PTDPUE[7:0] — Port D Input Pullup Enable Bits
Notes:
Reset:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Read:
Write:
Figure 17-14. Port D Input Pullup Enable Register (PTDPUE)
DDRD
These writable bits are software programmable to enable pullup
devices on an input port pin.
Freescale Semiconductor, Inc.
Bit
0
1
For More Information On This Product,
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin internal pullup disconnected
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
$003D
Bit 7
0
summarizes the operation of the port D pins.
Go to: www.freescale.com
PTD Bit
Input/Output (I/O) Ports
X
X
(1)
6
0
Table 17-5. Port D Pin Functions
Input, Hi-Z
I/O Pin
Output
Mode
5
0
(2)
4
0
Read/Write
DDRD[7:0]
DDRD[7:0]
Accesses
to DDRD
3
0
PTD[7:0]
2
0
Read
Accesses to PTD
Input/Output (I/O) Ports
Pin
1
0
Technical Data
PTD[7:0]
PTD[7:0]
Write
Bit 0
Port D
0
325
(3)