MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 111

• Manufacturer Part Number: MC68HC908JK3EMP
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
If V
(Table 9-1
clock input to OSC1. If PTB3 is high with V
monitor mode entry
divide-by-four of the clock input to OSC1. Holding the PTB3 pin low
when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if V
OSCOUT frequency is equal to the 2OSCOUT frequency, and OSC1
input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
Entering monitor mode with V
long as V
7. System Integration Module (SIM)
operation.)
If entering monitor mode without high voltage on IRQ1 and reset vector
being blank ($FFFE and $FFFF)
applied voltage is V
including the PTB3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ1 or the RST.
Figure
the reset vector is blank and IRQ1 = V
9.8304MHz is required for a baud rate of 9600.
DD
—
+V
Rev. 2.0
9-2. shows a simplified diagram of the monitor mode entry when
DD
HI
condition set 1), the bus frequency is a divide-by-two of the
is applied to IRQ1 and PTB3 is low upon monitor mode entry
+ V
Monitor ROM (MON)
HI
is applied to either the IRQ1 or the RST. (See
DD
(Table 9-1
), then all port B pin requirements and conditions,
DD
+V
DD
HI
condition set 2), the bus frequency is a
is applied to IRQ1. In this event, the
+ V
(Table 9-1
HI
for more information on modes of
DD
on IRQ1, the COP is disabled as
. An OSC1 frequency of
DD
condition set 3, where
+V
HI
applied to IRQ1 upon
Functional Description
Monitor ROM (MON)
Technical Data
Section
111