MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 62

• Manufacturer Part Number: MC68HC908JK3EMP
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Central Processor Unit (CPU)
6.4.5 Condition Code Register
Technical Data
62
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
V — Overflow Flag
H — Half-Carry Flag
I — Interrupt Mask
Reset:
Read:
Write:
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction
uses the states of the H and C flags to determine the appropriate
correction factor.
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Overflow
0 = No overflow
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
1 = Interrupts disabled
0 = Interrupts enabled
X = Indeterminate
Bit 7
V
X
Central Processor Unit (CPU)
Figure 6-6. Condition Code Register (CCR)
6
1
1
5
1
1
4
H
X
MC68H(R)C908JL3E/JK3E/JK1E
3
1
I
N
2
X
1
Z
X
MOTOROLA
—
Rev. 2.0
Bit 0
C
X