MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 84

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MC68HC908JK3EMP

Manufacturer Part Number
MC68HC908JK3EMP
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
System Integration Module (SIM)
7.4.2.1 Power-On Reset
Technical Data
84
2OSCOUT
OSCOUT
PORRST
OSC1
RST
IAB
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
CYCLES
4096
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive 2OSCOUT.
Internal clocks to the CPU and modules are held inactive for 4096
2OSCOUT cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the reset status register (RSR) is set and all other
bits in the register are cleared.
Figure 7-7. POR Recovery
System Integration Module (SIM)
CYCLES
32
CYCLES
32
MC68H(R)C908JL3E/JK3E/JK1E
$FFFE
$FFFF
MOTOROLA
Rev. 2.0

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