MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 95
MC68HC908JK3EMP
Manufacturer Part Number
MC68HC908JK3EMP
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3EMP.pdf
(226 pages)
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MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
Figure 7-16
EXITSTOPWAIT
NOTE: EXITSTOPWAIT =
2OSCOUT
R/W
—
IDB
IAB
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
RST
IDB
IAB
Rev. 2.0
IDB
IAB
Figure 7-16. Wait Recovery from Interrupt or Break
System Integration Module (SIM)
WAIT ADDR
last instruction.
$A6
Figure 7-17. Wait Recovery from Internal Reset
$A6
and
PREVIOUS DATA
Figure 7-15. Wait Mode Entry Timing
$6E0B
$A6
Figure 7-17
$6E0B
$A6
RST
pin OR CPU interrupt OR break interrupt
WAIT ADDR + 1
$A6
$A6
Cycles
show the timing for WAIT recovery.
$6E0C
32
NEXT OPCODE
$01
$00FF
Cycles
32
$0B
SAME
System Integration Module (SIM)
$00FE
SAME
$6E
RST VCT H
$00FD
SAME
Low-Power Modes
RST VCT L
SAME
Technical Data
$00FC
95
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