MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 175

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MC68HC908JK3EMP

Manufacturer Part Number
MC68HC908JK3EMP
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
14.4.2 Keyboard Status and Control Register
MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
Address:
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
Bits 7–4 — Not used
KEYF — Keyboard Flag Bit
Reset:
Read:
Write:
1. Configure the keyboard pins as outputs by setting the appropriate
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
Figure 14-3. Keyboard Status and Control Register (KBSCR)
These read-only bits always read as logic 0’s.
This read-only bit is set when a keyboard interrupt is pending on port-
A. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
DDRA bits in the data direction register A.
keyboard interrupt enable register.
Flags keyboard interrupt requests
Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
Rev. 2.0
$001A
Bit 7
0
0
Keyboard Interrupt Module (KBI)
= Unimplemented
6
0
0
5
0
0
4
0
0
KEYF
3
0
Keyboard Interrupt Module (KBI)
ACKK
2
0
0
Functional Description
IMASKK
1
0
Technical Data
MODEK
Bit 0
0
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