MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet - Page 141
MC68HC908JK3EMP
Manufacturer Part Number
MC68HC908JK3EMP
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JK3EMP.pdf
(226 pages)
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MC68H(R)C908JL3E/JK3E/JK1E
MOTOROLA
NOTE:
NOTE:
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
CHxMAX
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
When the TOVx bit is at logic one, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 10-8
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
TCHx
—
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
Rev. 2.0
OVERFLOW
Timer Interface Module (TIM)
shows, the CHxMAX bit takes effect in the cycle after it
COMPARE
PERIOD
OUTPUT
Figure 10-8. CHxMAX Latency
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
Timer Interface Module (TIM)
OVERFLOW
COMPARE
OUTPUT
Technical Data
OVERFLOW
I/O Registers
141
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