PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 139

• Manufacturer Part Number: PEF20525
• Description: 2 Channel Serial Optimized Communication Controller for HDLC/PPP
• Manufacturer: INFINEON [Infineon Technologies AG]

Data Sheet
Register 21
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 22
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
Power
VIS
PU
7
7
CCR0L
Channel Configuration Register 0 (Low Byte)
CCR0H
Channel Configuration Register 0 (High Byte)
PSD
6
6
read/write
00
Channel A
16
written by CPU;
read and evaluated by SEROCCO-H
read/write
00
Channel A
17
written by CPU;
read and evaluated by SEROCCO-H
H
H
H
H
misc.
Line Coding
SC(2:0)
5
5
0
Channel B
66
Channel B
67
H
H
TOE
5-139
4
4
SSEL
3
3
0
Register Description (CCR0L)
Clock Mode Selection
2
2
0
CM(2:0)
1
1
0
PEB 20525
PEF 20525
2000-09-14
0
0
0