PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 54

• Manufacturer Part Number: PEF20525
• Description: 2 Channel Serial Optimized Communication Controller for HDLC/PPP
• Manufacturer: INFINEON [Infineon Technologies AG]

3.2.3.4
The BRG is fed with an externally generated clock via pin RxCLK. Depending on the
value of bit ’SSEL’ in register
DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) or
delivers directly the receive and transmit clock (clock mode 3b). In the first case the
DPLL output clock is used as receive and transmit clock.
Figure 18
Data Sheet
Clock Mode 3 (3a/3b)
clock mode 3a
clock mode 3b
Clock Mode 3a/3b Configuration
Ctrl.
Ctrl.
DPLL
BRG
BRG
Ctrl.
Ctrl.
CCR0L
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
the BRG delivers either a reference clock for the
54
(tx clock monitor output)
(tx clock monitor output)
Functional Overview
clock supply
clock supply
1
1
PEB 20525
PEF 20525
2000-09-14