PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 28
PEF20525
Manufacturer Part Number
PEF20525
Description
2 Channel Serial Optimized Communication Controller for HDLC/PPP
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF20525.pdf
(252 pages)
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2.3
Table 1
Pin No.
P-
LFBGA-
80-2
-
-
-
-
-
-
-
-
C8
D9
D6
D8
E8
F9
F7
E6
J2
G3
J3
H4
J4
H5
G5
Data Sheet
P-TQFP-
100-3
81
80
79
78
75
74
73
72
67
66
65
64
61
60
59
58
29
30
31
32
36
37
38
Pin Definitions and Functions
Microprocessor Bus Interface
Symbol In (I)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A7
A6
A5
A4
A3
A2
A1
Out (O)
I/O
I
I
I
I
I
I
I
Function
Data Bus
The data bus lines are bi-directional tri-state lines
which interface with the system’s data bus.
The SEROCCO-H in the P-LFBGA-80-2 package
does not support 16-bit bus modes.
Address Bus
These pins connect to the system’s address bus
to select one of the internal registers for read or
write.
28
Pin Descriptions
PEB 20525
PEF 20525
2000-09-14
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