PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 50
PEF20525
Manufacturer Part Number
PEF20525
Description
2 Channel Serial Optimized Communication Controller for HDLC/PPP
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF20525.pdf
(252 pages)
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The clocking concept is illustrated in a block diagram manner in the following figure:
Additional control signals are not illustrated (please refer to the detailed clock mode
descriptions below).
Figure 14
Data Sheet
Clock Supply Overview
settings controlled by:
register CCR0, bit field 'CM'
selects the clock mode number
register CCR0, bit 'SSEL'
selects the additional a/b option
TTL
Oscillator
or
CRYSTAL
3a
7a
Transmitter
0b
3b
7b
DPLL
2b
6b
f
f
DPLL
TRM
1
5a
0b
6a/b
7a/b
50
0a
2a
6a
4
5b
BRG
f
BRG
2a/b
3a/b
16:1
f
BRG/16
2a/b
3a
6a/b
7a
Receiver
3b
7b
f
RxCLK
f
REC
0a/b
1
5a/b
4
Functional Overview
f
TxCLK
PEB 20525
PEF 20525
2000-09-14
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