PEF20525 INFINEON [Infineon Technologies AG], PEF20525 Datasheet - Page 81

• Manufacturer Part Number: PEF20525
• Description: 2 Channel Serial Optimized Communication Controller for HDLC/PPP
• Manufacturer: INFINEON [Infineon Technologies AG]

3.5
For certain events in SEROCCO-H an interrupt can be generated, requesting the CPU
to read status information from SEROCCO-H. The interrupt line INT/INT is asserted with
the output characteristics programmed in bit field ’IPC(1..0)’ in register
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Since only one interrupt request output is provided, the cause of an interrupt must be
determined by the CPU by reading the interrupt status registers (GSTAR, ISR0, ISR1,
ISR2, DISR, GPISL/GPISH).
Figure 38
Each interrupt indication of registers ISR0, ISR1, ISR2,
selectively unmasked by resetting the corresponding bit in the corresponding mask
registers IMR0, IMR1, IMR2,
on the selected serial mode.
If bit ’VIS’ in register
interrupt status registers ISR0..ISR2. Interrupts masked in registers
generate an interrupt though. A read access to the interrupt status registers clears the
bits.
A global interrupt mask bit (bit ’GIM’ in register GMODE) suppresses interrupt generation
at all. To enable the interrupt system after reset, this bit must be set to ’0’.
Data Sheet
GPIM
(open drain/push pull, active low/high).
Interrupt Architecture
GPIS
Interrupt Status Registers
DIMR
DISR
CCR0L
GSTAR
GPI
DIMR
is set to ’1’, masked interrupt status bits are visible in the
DMI
and GPIML/GPIMH. Use of these registers depends
Channel A
ISA2
Channel B
IMR2 (ch A)
81
ISR2 (ch A)
ISA1
IMR1 (ch A)
ISR1 (ch A)
ISA0
IMR0 (ch A)
DISR
ISR0 (ch A)
ISB2
and
Functional Overview
GPISL/GPISH
ISB1
IMR0..IMR2
“GMODE” on
ISB0
PEB 20525
PEF 20525
2000-09-14
will not
can be