MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet - Page 100

• Manufacturer Part Number: MC9RS08KA1
• Description: RS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 12 Development Support
12.3.3
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD to answer the SYNC
request pulse. If the rising edge is not detected, the target will keep waiting indefinitely, without any
timeout limit. When a rising edge on BKGD occurs after a valid SYNC request, the BDC will drive the
BKGD pin low for exactly 128 BDC cycles.
Consider now the case where the host returns BKGD to logic 1 before 128 cycles. This is interpreted as a
valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred as a soft-reset to the BDC.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieving after the timeout has
occurred. A soft-reset is also used to end a READ_BLOCK or WRITE_BLOCK command.
The following describes the actual bit-time requirements for a host to guarantee logic 1 or 0 bit
transmission without the target timing out or interpreting the bit as a SYNC command:
100
SPEEDUP PULSE
PERCEIVED START
•
•
TO BKGD PIN
TARGET MCU
(TARGET MCU)
HOST DRIVE
DRIVE AND
BDC CLOCK
OF BIT TIME
To send a logic 0, BKGD must be kept low for a minimum of 12 BDC cycles and up to 511 BDC
cycles except for the first bit of a command sequence, which will be detected as a SYNC request.
To send a logic 1, BKGD must be held low for at least four BDC cycles, be released by the eighth
cycle, and be held high until at least the sixteenth BDC cycle.
BKGD PIN
SYNC and Serial Communication Timeout
Figure 12-5. BDM Target-to-Host Serial Bit Timing (Logic 0)
MC9RS08KA2 Series Data Sheet, Rev. 3
10 CYCLES
HOST SAMPLES BKGD PIN
10 CYCLES
HIGH IMPEDANCE
SPEEDUP
PULSE
EARLIEST START
OF NEXT BIT
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