MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet - Page 60

• Manufacturer Part Number: MC9RS08KA1
• Description: RS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 8 Central Processor Unit (RS08CPUV1)
Other instructions may be executed between the test and the conditional branch as long as the only
instructions used are those which do not disturb the CCR bits that affect the conditional branch. For
instance, a test is performed in a subroutine or function and the conditional branch is not executed until the
subroutine has returned to the main program. This is a form of parameter passing (that is, information is
returned to the calling program in the condition code bits).
Z — Zero Flag
C — Carry
8.2.5
This 8-bit indexed data register allows the user to access the data in the direct page address space indexed
by X. This register resides at the memory mapped location $000E. For details on the D[X] register, please
refer to
8.2.6
This 8-bit index register allows the user to index or address any location in the direct page address space.
This register resides at the memory mapped location $000F. For details on the X register, please refer to
Section 8.3.8, “Indexed Addressing Mode (IX, Implemented by Pseudo
60
The Z bit is set to indicate the result of an operation was $00.
Branch if equal (BEQ) and branch if not equal (BNE) are simple branches that branch based solely
on the value in the Z bit. All load, store, move, arithmetic, logical, shift, and rotate instructions
cause the Z bit to be updated.
After an addition operation, the C bit is set if the source operands were both greater than or equal
to $80 or if one of the operands was greater than or equal to $80 and the result was less than $80.
This is equivalent to an unsigned overflow. A subtract or compare performs a subtraction of a
memory operand from the contents of a CPU register so after a subtract operation, the C bit is set
if the unsigned value of the memory operand was greater than the unsigned value of the CPU
register. This is equivalent to an unsigned borrow or underflow.
Branch if carry clear (BCC) and branch if carry set (BCS) are branches that branch based solely on
the value in the C bit. The C bit is also used by the unsigned branches BLO and BHS. Add, subtract,
shift, and rotate instructions cause the C bit to be updated. The branch if bit set (BRSET) and
branch if bit clear (BRCLR) instructions copy the tested bit into the C bit to facilitate efficient
serial-to-parallel conversion algorithms. Set carry (SEC) and clear carry (CLC) allow the carry bit
to be set or cleared directly. This is useful in combination with the shift and rotate instructions and
for routines that pass status information back to a main program, from a subroutine, in the C bit.
The C bit is included in shift and rotate operations so those operations can easily be extended to
multi-byte operands. The shift and rotate operations can be considered 9-bit shifts that include an
8-bit operand or CPU register and the carry bit of the CCR. After a logical shift, C holds the bit that
was shifted out of the 8-bit operand. If a rotate instruction is used next, this C bit is shifted into the
operand for the rotate, and the bit that gets shifted out the other end of the operand replaces the
value in C so it can be used in subsequent rotate instructions.
Section 8.3.8, “Indexed Addressing Mode (IX, Implemented by Pseudo
Indexed Data Register (D[X])
Index Register (X)
MC9RS08KA2 Series Data Sheet, Rev. 3
Instructions).”
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