MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet - Page 47

• Manufacturer Part Number: MC9RS08KA1
• Description: RS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

6.3
This section provides information about the registers associated with the parallel I/O ports that are used
for pin control functions.
Refer to tables in
This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided
equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.3.1
The pins associated with port A are controlled by the registers provided in this section. These registers
control the pin pullup/pulldown and slew rate of the port A pins independent of the parallel I/O registers.
6.3.1.1
An internal pulling device can be enabled for each port pin by setting the corresponding bit in the pulling
device enable register (PTAPEn). The pulling device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral output function regardless of the state of the
Freescale Semiconductor
PTADD[5:4,1:0]
PTAD[5:0]
Reset:
Field
5:0
5:4,1:0
Field
W
R
Pin Control Registers
Port A Pin Control Registers
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all
bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding
MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullup/pulldowns disabled.
0
Internal Pulling Device Enable
7
0
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read
for PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Chapter 4,
0
0
6
Figure 6-3. Port A Data Direction Register (PTADD)
“Memory,” for the absolute address assignments of the pin control registers.
Table 6-2. PTADD Register Field Descriptions
Table 6-1. PTAD Register Field Descriptions
PTADD5
MC9RS08KA2 Series Data Sheet, Rev. 3
0
5
PTADD4
0
4
Description
Description
3
0
0
Chapter 6 Parallel Input/Output Control
0
2
0
PTADD1
0
1
PTADD0
0
0
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