MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet - Page 72

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MC9RS08KA1

Manufacturer Part Number

MC9RS08KA1

Description

RS08 Microcontrollers

Manufacturer

FREESCALE [Freescale Semiconductor, Inc]

Datasheets

1.MC9RS08KA2.pdf (136 pages)

2.MC9RS08KA1.pdf (136 pages)

3.MC9RS08KA1.pdf (132 pages)

4.MC9RS08KA1.pdf (132 pages)

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Current page: 72 of 136
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Chapter 8 Central Processor Unit (RS08CPUV1)

72

LOW

INH

IMM

DIR

EXT

DD

HIGH

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

BRCLR0

BRCLR1

BRCLR2

BRCLR3

BRCLR4

BRCLR5

BRCLR6

BRCLR7

BRSET0

BRSET1

BRSET2

BRSET3

BRSET4

BRSET5

BRSET6

BRSET7

Inherent

Immediate

Direct

Extended

Direct-Direct

DIR

0

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Gray box is decoded as illegal instruction

BSET0

BCLR0

BSET1

BCLR1

BSET2

BCLR2

BSET3

BCLR3

BSET4

BCLR4

BSET5

BCLR5

BSET6

BCLR6

BSET7

BCLR7

DIR

1

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

REL

SRT

TNY

IMD

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

TNY

INC

INC

INC

INC

INC

INC

INC

INC

INC

INC

INC

INC

INC

INC

INC

INC

2

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

Relative

Short

Tiny

Immediate-Direct

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

2

3

2

2

2

2

1

1

2

3

2

3

2

DIR/REL

CBEQ

DBNZ

BCC

BEQ

DEC

MOV

BRA

BCS

BNE

CLC

SEC

CLR

INC

3

REL

REL

REL

REL

REL

IMD

DIR

INH

INH

DIR

DIR

DIR

DIR

3

5

3

3

3

3

1

1

5

6

5

4

3

3

1

1

1

1

1

1

1

1

2

1

3

1

CBEQA

DBNZA

COMA

RORA

ROLA

DECA

CLRA

LSRA

LSLA

INCA

MOV

SHA

SLA

INH

4

IMM

INH

INH

INH

INH

INH

INH

INH

INH

INH

INH

INH

DD

MC9RS08KA2 Series Data Sheet, Rev. 3

4

1

1

1

1

1

1

1

1

4

1

5

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

DEC

TNY

5

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

Table 8-2. Opcode Map

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

TNY

6

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

SUB

TNY

7

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

TNY

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

SRT

8

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

Low Byte of Opcode in Hexadecimal

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

SRT

9

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

High Byte of Opcode in Hexadecimal

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

2

1

1

IMM/INH

STOP

WAIT

CMP

EOR

ORA

NOP

SUB

SBC

AND

ADC

ADD

BSR

LDA

A

IMM

IMM

IMM

IMM

IMM

IMM

IMM

IMM

IMM

REL

INH

INH

INH

2+

2+

2

2

2

2

2

2

2

2

2

1

3

2

2

2

2

2

2

2

2

2

2

3

3

1

1

DIR/EXT

BGND

CMP

SUB

SBC

AND

EOR

ADC

ORA

ADD

LDA

JMP

JSR

RTS

STA

B

EXT

EXT

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

DIR

INH

INH

5+

3

3

3

3

3

3

3

3

3

3

4

4

3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Freescale Semiconductor

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

SRT

C

0

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

SUB

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

LDA

SRT

D

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

DIR

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

3

B

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

RS08 Cycles

Opcode Mnemonic

Number of Bytes /

Addressing Mode

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

SRT

E

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

STA

SRT

F

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

SRT

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

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