MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet - Page 37

• Manufacturer Part Number: MC9RS08KA1
• Description: RS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

and ACMP are still available to wake the CPU from wait or stop mode. It is the responsibility of the user
application to poll the corresponding module to determine the source of wakeup.
Each wakeup source of the module is associated with a corresponding interrupt enable bit. If the bit is
disabled, the interrupt source is gated, and that particular source cannot wake the CPU from wait or stop
mode. However, the corresponding interrupt flag will still be set to indicate that an external wakeup event
has occurred.
The system interrupt pending register (SIP1) indicates the status of the system pending interrupt. When
the read-only bit of the SIP1 is enabled, it shows there is a pending interrupt to be serviced from the
indicated module. Writing to the register bit has no effect. The pending interrupt flag will be cleared
automatically when the all corresponding interrupt flags from the indicated module are cleared.
5.6
The MC9RS08KA2 Series includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and an LVD circuit with a predefined trip voltage. The LVD
circuit is enabled with LVDE in SPMSC1. The LVD is disabled upon entering stop mode unless LVDSE
is set in SPMSC1. If LVDSE and LVDE are both set, the current consumption in stop with the LVD enabled
will be greater.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU
in reset until the supply has risen above the V
following a POR.
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level V
reset or POR.
5.6.3
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), LVDF in SPMSC1 will be set and an LVD interrupt
request will occur.
5.7
The real-time interrupt function can be used to generate periodic interrupts. The RTI is driven from either
the 1-kHz internal clock reference or the trimmed 32-kHz internal clock reference from the ICS module.
The 32-kHz internal clock reference is divided by 32 by the RTI logic to produce a trimmed 1-kHz clock
Freescale Semiconductor
Low-Voltage Detect (LVD) System
Real-Time Interrupt (RTI)
Power-On Reset Operation
LVD Reset Operation
LVD Interrupt Operation
LVD
MC9RS08KA2 Series Data Sheet, Rev. 3
. The LVD bit in the SRS register is set following either an LVD
LVD
level. Both the POR bit and the LVD bit in SRS are set
Chapter 5 Resets, Interrupts, and General System Control
POR
level, the
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