MC9RS08KA1 FREESCALE [Freescale Semiconductor, Inc], MC9RS08KA1 Datasheet - Page 102

• Manufacturer Part Number: MC9RS08KA1
• Description: RS08 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 12 Development Support
12.4.2
This 16-bit register holds the 14-bit address for the hardware breakpoint in the BDC. The BKPTEN and
FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. However, because READ_BKPT and WRITE_BKPT are non-intrusive commands,
they could be executed even while the user program is running. For additional information about setup and
use of the hardware breakpoint logic in the BDC, refer to the RS08 Family Reference Manual.”
102
BKPTEN
Field
WSF
FTS
WS
5
4
2
1
BDC Breakpoint Match Register
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored
0 BDC breakpoint disabled.
1 BDC breakpoint enabled.
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register
causes the fetched opcode to be tagged
the CPU enters active background mode rather than executing the tagged opcode
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work
background mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program
re-execute the wait or stop instruction
0 Memory access did not conflict with a wait or stop instruction.
1 Memory access command failed because the CPU entered wait or stop mode.
instruction.
opcode).
background became active).
active background mode.
Table 12-1. BDCSCR Register Field Descriptions (continued)
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MC9RS08KA2 Series Data Sheet, Rev. 3
When FTS = 0, a match between the CPU address bus and the BDCBKPT register
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)
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If this tagged opcode ever reaches the end of the instruction queue,
(Typically, the host would restore CPU registers and stack values and
Description
.
Whenever the host forces the target MCU into active
.
The usual recovery strategy is to issue a
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