LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 148
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 148 of 371
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General-Purpose Input/Outputs (GPIOs)
148
Reset
Type
Reset
Type
Bit/Field
31:8
GPIO Primecell Identification 2 (GPIOPCellID2)
Offset 0xFF8
7:0
RO
RO
31
15
0
0
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit
wide registers, that can conceptually be treated as one 32-bit register. The register is used as a
standard cross-peripheral identification system.
RO
RO
30
14
0
0
reserved
Name
CID2
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x05
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification
system.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
CID2
RO
RO
19
0
3
0
RO
RO
18
0
2
1
April 27, 2007
RO
RO
17
0
1
0
RO
RO
16
0
0
1
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