LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 267
![no-image](/images/no-image-200.jpg)
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 267 of 371
- Download datasheet (3Mb)
April 27, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
UART Primecell Identification 0 (UARTPCellID0)
Offset 0xFF0
7:0
RO
RO
31
15
0
0
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the
reset values.
RO
RO
30
14
0
0
reserved
Name
CID0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0x0D
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification
system.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
CID0
RO
RO
19
0
3
1
LM3S328 Data Sheet
RO
RO
18
0
2
1
RO
RO
17
0
1
0
RO
RO
16
0
0
1
267
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