LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 330
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 330 of 371
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Inter-Integrated Circuit (I2C) Interface
330
Reset
Reset
Type
Type
Bit/Field
I2C Master Interrupt Clear (I2CMICR)
Offset 0x01C
31:1
0
RO
RO
31
15
0
0
Register 8: I
This register clears the raw interrupt.
RO
RO
30
14
0
0
reserved
Name
RO
RO
29
13
0
0
IC
2
RO
RO
C Master Interrupt Clear (I2CMICR), offset 0x01C
28
12
0
0
RO
RO
27
11
0
0
Type
WO
RO
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
Preliminary
reserved
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of
1 clears the interrupt; otherwise, a write of 0 has no affect
on the interrupt state. A read of this register returns no
meaningful data.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
April 27, 2007
RO
RO
17
0
1
0
WO
RO
IC
16
0
0
0
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