LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 226
![no-image](/images/no-image-200.jpg)
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 226 of 371
- Download datasheet (3Mb)
Analog-to-Digital Converter (ADC)
226
Reset
Reset
Type
Type
Bit/Field
31:13
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
Offset 0x04C
11:9
7:4
3:0
12
8
RO
RO
31
15
0
0
reserved
Register 14: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C
This register provides a window into the Sample Sequencer FIFO 0, providing full/empty status
information as well as the positions of the head and tail pointers. The reset value of 0x100
indicates an empty FIFO.
RO
RO
30
14
0
0
reserved
reserved
EMPTY
HPTR
Name
TPTR
FULL
RO
RO
29
13
0
0
FULL
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
reserved
RO
RO
26
10
0
0
Reset
0
0
1
0
0
0
RO
RO
25
0
9
0
Preliminary
EMPTY
Description
Reserved bits return an indeterminate value, and should never
be changed.
When set, indicates that the FIFO is currently full.
Reserved bits return an indeterminate value, and should never
be changed.
When set, indicates that the FIFO is currently empty.
This field contains the current "head" pointer index for the
FIFO, that is, the next entry to be written.
This field contains the current "tail" pointer index for the FIFO,
that is, the next entry to be read.
RO
RO
24
0
8
1
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
HPTR
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
TPTR
April 27, 2007
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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