LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 225
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 225 of 371
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April 27, 2007
Reset
Reset
Type
Type
Bit/Field
31:10
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Offset 0x048
9:0
RO
RO
31
15
0
0
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
This register contains the conversion results for samples collected with Sample Sequencer 0.
Reads of this register return conversion result data in the order sample 0, sample 1, and so on,
until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow
conditions are registered in the ADCOSTAT and ADCUSTAT registers.
RO
RO
30
14
0
0
reserved
Name
DATA
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
Conversion result data.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
DATA
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S328 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
225
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