LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 327
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 327 of 371
- Download datasheet (3Mb)
April 27, 2007
Reset
Reset
Type
Type
Bit/Field
I2C Master Interrupt Mask (I2CMIMR)
Offset 0x010
31:1
0
RO
RO
31
15
0
0
Register 5: I
This register controls whether a raw interrupt is promoted to a controller interrupt.
RO
RO
30
14
0
0
reserved
Name
RO
RO
29
13
0
0
IM
2
RO
RO
C Master Interrupt Mask (I2CMIMR), offset 0x010
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
Preliminary
reserved
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls whether a raw interrupt is promoted to a
controller interrupt. If set, the interrupt is not masked and
the interrupt is promoted; otherwise, the interrupt is
masked.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S328 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
R/W
IM
RO
16
0
0
0
327
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