LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 74
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 74 of 371
- Download datasheet (3Mb)
System Control
74
Reset
Reset
Type
Type
Bit/Field
31:17
15:4
Software Reset Control 0 (SRCR0)
Offset 0x040
2:0
16
3
RO
RO
31
15
0
0
Register 10: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register (see
page 66).
RO
RO
30
14
0
0
reserved
reserved
reserved
Name
WDT
ADC
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
RO
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
9
0
0
0
0
0
0
Preliminary
reserved
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Reset control for the ADC unit.
Reserved bits return an indeterminate value, and should
never be changed.
Reset control for the Watchdog unit.
Reserved bits return an indeterminate value, and should
never be changed.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
WDT
RO
R/W
19
0
3
0
RO
RO
18
0
2
0
reserved
April 27, 2007
RO
RO
17
0
1
0
ADC
R/W
RO
16
0
0
0
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