LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 307
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LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 307 of 371
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14.2.1
14.2.1.1
14.2.1.2
14.2.1.3
April 27, 2007
Figure 14-2. I
I
The I
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line.
Data Transfers
Both the SDA and SCL lines are bi-directional, connected to the positive supply via pull-up
resistors. The bus is idle or free, when both lines are High. The output devices (pad drivers) must
have an open-drain configuration. Data on the I
in Standard mode and up to 400 Kbps in Fast mode.
Data Validity
The data on the SDA line must be stable during the High period of the clock. The data line can only
change when the clock SCL is in its Low state (see Figure 14-3).
Figure 14-3. Data Validity During Bit Transfer on the I
START and STOP Conditions
The protocol of the I
SDA line while the SCL is High is a START condition. A Low-to-High transition on the SDA line
while SCL is High is defined as a STOP condition. The bus is considered busy after a START
condition. The bus is considered free after a STOP condition. See Figure 14-4.
Figure 14-4. START and STOP Conditions
2
C Bus Functional Overview
2
C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
SDA
SCL
2
C Bus Configuration
condition
START
SDA
SCL
2
C bus defines two states: START and STOP. A High-to-Low transition on the
SDA
SCL
I2CSCL I2CSDA
Stellaris TM
Preliminary
Data line
R PUP
stable
with I 2 C Interface
3rd Party Device
SCL
R PUP
2
Chan ge
allowed
of data
C bus can be transferred at rates up to 100 Kbps
SDA
with I 2 C Interface
2
3rd Party Device
C Bus
SCL
SDA
condition
I 2 C Bus
STOP
LM3S328 Data Sheet
SDA
SCL
307
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