AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 11

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
A
Notes:
1. Addresses are A21–A0 in double word mode (WORD# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Word/Double Word Configuration
The WORD# pin controls whether the device data I/O
pins operate in the word or double word configuration.
If the WORD# pin is set at V
word configuration, DQ31–DQ0 are active and con-
trolled by CE# and OE#.
If the WORD# pin is set at V
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ30–DQ16 are tri-stated, and the DQ31 pin is
used as an input for the least significant address bit
(LSB) function, which is named A-1.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
whether the device outputs array data in words or dou-
ble words.
10
Read
Write
Standby
Output Disable
Reset
Temporary Sector
Unprotect (High Voltage)
IN
= Address In, D
Protection” section.
Operation
IN
= Data In, D
IH
. The WORD# pin determines
IL
V
0.3 V
CE#
, H = Logic High = V
CC
X
X
L
L
L
IH
IL
OUT
, the device is in double
Table 1. Am29PDL128G Device Bus Operations
, the device is in word
OE#
H
X
H
X
X
L
IL
= Data Out
. CE# is the power
WE# RESET#
H
X
H
X
X
L
P R E L I M I N A R Y
IH
, V
V
0.3 V
V
CC
H
H
H
L
ID
ID
Am29PDL128G
= 11.5–12.5 V, V
IH
WP#
), A21–A-1 in word mode (WORD# = V
X
X
X
X
X
X
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC
specifications and to Figure 11 for the timing diagram.
I
tive current specification for reading array data.
Random Read (Non-Page Read)
Address access time (t
stable addresses to valid output data. The chip enable
access time (t
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
CC1
in the DC Characteristics table represents the ac-
HH
Addresses
(Note 1)
= 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
Table 1
A
A
A
X
X
X
IN
IN
IN
CE
lists the device bus operations, the in-
Read-Only Operations
) is the delay from the stable ad-
WORD#
High-Z
High-Z
High-Z
= V
D
D
D
OUT
IN
IN
IH
ACC
DQ31–DQ16
) is equal to the delay from
High-Z, DQ31 = A-1
DQ30–DQ16 =
IL
WORD#
High-Z
High-Z
High-Z
).
= V
X
IL
table for timing
July 29, 2002
DQ15–
High-Z
High-Z
High-Z
D
DQ0
D
D
OUT
IN
IN