AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 43

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

Legend:
DYB = Dynamic Protection Bit
SSA = SecSi Sector Address (A6:A0) is (0011010).
PD[1:0] = Program Data. Password written in 2 portions.
PPB = Persistent Protection Bit
PWA = Password Address. A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read Data DQ0 for protection indicator bit.
1.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. Reset command returns device to reading array.
6. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate
7. Data is latched on rising edge of WE#.
8. Entire command sequence must be executed for each portion of
42
Command (Notes)
Reset
SecSi Sector Entry
SecSi Sector Exit
SecSi Protection Bit Program (5, 6)
Password Program (5, 7, 8)
Password Verify (8, 9)
Password Unlock (7, 10, 11)
PPB Program (6, 12)
All PPB Erase (13, 14)
PPB Lock Bit Set
PPB Lock Bit Status (15)
DYB Write (7)
DYB Erase (7)
DYB or PPB Status
PPMLB Program (6,12)
PPMLB Status (5)
SPMLB Program (6,12)
SPMLB Status (5)
See
write operations.
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle
6, entire command sequence must be issued and verified again.
password.
Table 1
for description of bus operations.
Table 15. Sector Protection Command Definitions (x32 Mode)
1
3
4
6
4
4
4
6
6
3
4
4
4
4
6
4
6
4
Addr Data Addr Data
XXX
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
F0
P R E L I M I N A R Y
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
Am29PDL128G
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
(BA)555
(BA)555
(BA)555
Addr
555
555
555
555
555
555
555
555
555
555
555
555
555
555
RD(1) = Read Data DQ1 for PPB Lock bit status.
SA = Sector Address where security command applies. Address bits
A21:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010) (Note 17)
EP = PPB Erase Address (A6:A0) is (1111010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
9. Command sequence returns FFh if PPMLB is set.
10. Password is written over four consecutive cycles at addresses
11. A 2 µs timeout is required between any two portions of password.
12. A 100 µs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
15. DQ1 = 1 if PPB locked, 0 if unlocked.
16. For all other parts that use the Persistant Protection Bit (axcluding
0-3.
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, entire command
sequence must be issued and verified again. Before issuing
erase command, all PPBs should be programmed to prevent
PPBs overerasure.
PDL640G), the WP address is 000010.
Data
Bus Cycles (Notes 1-4)
C8
88
90
60
38
28
60
60
78
58
48
48
58
60
60
60
60
PWA[0-1] PWD[0-1]
PWA[0-1] PWD[0-1]
(SA)WP
XX[0-1]
(SA)EP
Addr
SSA
XX
SA
SA
SA
SA
PL
PL
SL
SL
PD[0-1]
RD(1)
RD(0)
RD(0)
RD(0)
Data
X1
X0
00
68
68
60
68
68
(SA)WP
(SA)EP
Addr
SSA
PL
SL
Data
48
48
40
48
48
July 29, 2002
(SA)WP RD(0)
(SA)WP RD(0)
Addr
XX
XX
XX
RD(0)
RD(0)
RD(0)
Data