AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 46

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7.
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
complete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether a bank is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then that bank returns to the
read mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then
the bank returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ31–DQ0 (or DQ15–DQ0 for word mode) on the fol-
lowing read cycles. Just prior to the completion of an
Embedded Program or Erase operation, DQ7 may
c h a n g e a s y n c h r o n o u s l y w i t h D Q 3 1 – D Q 1 6
(DQ15–DQ0 for word mode) while Output Enable
(OE#) is asserted low. That is, the device may change
from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 out-
put, it may read the status or valid data. Even if the de-
July 29, 2002
Table 18
and the following subsections describe the
P R E L I M I N A R Y
Am29PDL128G
vice has completed the program or erase operation
a n d D Q7 h a s v a l i d d a ta , th e d a t a o u t p u ts o n
D Q31– DQ0 m ay be s ti ll inv ali d. Valid da ta o n
DQ31–DQ0 (or DQ15–DQ0 for word mode) will ap-
pear on successive read cycles.
Table 18
Figure 5 shows the Data# Polling algorithm. Figure 20
in the
Polling timing diagram.
Notes:
1. VA = Valid address for programming. During a sector
2. DQ7 should be rechecked even if DQ5 = “1” because
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
DQ7 may change simultaneously with DQ5.
No
AC Characteristics
Figure 5. Data# Polling Algorithm
shows the outputs for Data# Polling on DQ7.
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
No
Yes
No
section shows the Data#
Yes
Yes
PASS
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