AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 68

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

REVISION SUMMARY
Revision A (October 29, 2001)
Initial release.
Revision A+1 (November 13, 2001)
Simultaneous Operation Block Diagram
Added drawing.
Table
Corrected data for 4Dh and 4Eh addresses (dou-
ble-word mode).
Physical Dimensions
Added LAB080 package drawing.
Revision A+2 (February 8, 2002)
Global
Added 90 ns speed option. At this speed, t
and t
programming time to 8.6 µs, and typical double word
programming time to 12.6 µs.
Simultaneous Operation Block Diagram
Deleted BYTE# input.
Revision B (April 26, 2002)
Global
Added 70R (regulated voltage range) to speed op-
tions.
Ordering Information
Added “V” to package marking.
Device Bus Operations
Corrected sector size references in sector address ta-
ble.
Password Protection Mode section: Clarified that first
8 bytes of SecSi Sector should be reserved for the
password. Added description of using password and
SecSi Sector concurrently.
SecSi Sector Flash Memory Region
Added section on using password and SecSi Sector
concurrently.
Table
Corrected data for addresses 4D and 4Eh.
Command Definitions
Deleted PPB Status Command section.
Password Program Command section: Modified first
paragraph.
July 29, 2002
OH
13,
13,
is 5 ns. For all speeds, changed typical word
Primary Vendor-Specific Extended Query
Primary Vendor-Specific Extended Query
P R E L I M I N A R Y
DF
is 30 ns
Am29PDL128G
Password Unlock Command section: Modified second
paragraph.
PPB Lock Bit Set Command section: Modified entire
section.
Substantial modifications were made to the command
definitions tables and notes, including the following:
deleted the PPB Status command sequence; added
bank address requirements to SecSi Sector com-
mand; separated memory array and sector protection
command sequences for easier reference.
DC Characteristics
In Note 1 of the CMOS Compatible table, changed typ-
ical I
cal and maximum read currents, added currents for 10
MHz operation. Added specifications for intra-page
read current. Changed I
Revision B+1 (June 7, 2002)
Global
Changed data sheet status from Advance Information
to Preliminary.
AC Characteristics: Read-only Operations table
Changed t
Changed t
AC Characteristics: Erase and Program Operations
table, Alternate CE# Controlled Erase and Program
Operations table
Changed t
Changed t
Changed t
values from t
Erase and Programming Performance
Added or modified typical and maximum values to all
parameters in table except for typical sector erase
time.
Revision B+2 (July 29, 2002)
Global
Changed Simultanous Operation Flash to Simultanous
Read/ Write Flash.
Changed all references to DPB to DYB.
BGA Package Capacitance
Replaced TSOP Pin Capacitance with FBGA Capaci-
tance data.
Table 7. Autoselect Codes (High Voltage Method)
Changed the A5 to A4 and A3 Sector Protection Verifi-
cation fields from L to H.
CC
current from 2 to 4mA/MHz. Changed I
OH
OEPH
A SO
O E
DS
WHWH1
for 70 ns speeds from 4 to 5 ns.
for 80 ns speed from 45 to 35 ns.
for 90 ns speed from 40 to 35 ns.
from 20 to 10 ns. Changed all typical
for 70 ns speed from 15 to 12 ns.
.
CC6
typical current to 30 mA.
CC1
typi-
67