AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 2

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

Am29PDL128G
128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous
Read/ Write Flash Memory with VersatileIO
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
PERFORMANCE CHARACTERISTICS
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
128Mbit Page Mode device
— Word (16-bit) or double word (32-bit) mode selectable via
— Page size of 8 words/4 double words: Fast page read access
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and program
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
— Organized as two 16 Mbit banks (Bank 1 & 4) and two 48
VersatileI/O
— Output voltage generated and input voltages tolerated on the
SecSi (Secured Silicon) Sector region
— 128 words (64 double words) accessible through a
Both top and bottom boot blocks in one device
Manufactured on 0.17 µm process technology
20-year data retention at 125°C
Minimum 1 million write cycle guarantee per sector
High Performance
— Page access times as fast as 25 ns
— Random access times as fast as 70 ns
Power consumption (typical values at 10 MHz)
— 38 mA active read current
— 17 mA program/erase current
— 1.5 µA typical standby mode current
WORD# input
from random locations within the page
operations for battery-powered applications
executing erase/program functions in another bank
per device
Mbit banks (Bank 2 & 3)
device is determined by the voltage on the V
command sequence
PRELIMINARY
TM
(V
IO
) Control
Refer to AMD’s Website (www.amd.com) for the latest information.
IO
pin
SOFTWARE FEATURES
HARDWARE FEATURES
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
WP# (Write Protect) input
— At V
— At V
— An internal pull up to Vcc is provided
Persistent Sector Protection
— A command sector protection method to lock combinations
— Sectors can be locked and unlocked in-system at V
Password Sector Protection
— A sophisticated sector protection method to lock
ACC (Acceleration) input provides faster programming
times in a factory setting
Package options
— 80-ball Fortified BGA
TM
host software to easily reconfigure for different Flash devices
operations in other sectors of same bank
program command sequences
cycle completion
regardless of sector protect/unprotect status
of individual sectors and sector groups to prevent program or
erase operations within that sector
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
Control
IL
IH
, protects the two top and two bottom sectors,
, allows removal of sector protection
Publication# 25685
Issue Date: July 29, 2002
Rev: B Amendment/+2
CC
level