AM29PDL128G70 SPANSION [SPANSION], AM29PDL128G70 Datasheet - Page 36

• Manufacturer Part Number: AM29PDL128G70
• Description: 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

until the system issues the four-cycle Exit SecSi Sec-
tor command sequence. The Exit SecSi Sector com-
m an d se q u e n c e r e t ur n s t he d e v i c e to n o rm a l
operation. The SecSi Sector is not accessible when
the device is executing an Embedded Program or em-
bedded Erase algorithm. Tables
address and data requirements for both command se-
quences. See also “SecSi™ (Secured Silicon) Sector
Flash Memory Region” for further information.
Double Word/Word Program Command
Sequence
The system may program the device by double word
or word, depending on the state of the WORD# pin.
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Tables
address and data requirements for the program com-
mand sequence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the
Status
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read will show that the
July 29, 2002
section for information on these status bits.
15
14
and
and
Write Operation
17
16
P R E L I M I N A R Y
show the
show the
Am29PDL128G
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram data to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Tables
for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the read mode.
The device offers accelerated program operations
through the ACC pin. When the system asserts V
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation. Note that the
ACC pin must not be at V
accelerated programming, or device damage may re-
sult. In addition, the ACC pin must not be left floating
or unconnected; inconsistent behavior of the device
may result.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the
table in the AC Characteristics section for parameters,
and
Figure 16
for timing diagrams.
14
Erase and Program Operations
and
HH
16
any operation other than
show the requirements
HH
35
on