SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 12

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SDA5523

Manufacturer Part Number
SDA5523
Description
SDA55xx TVText Pro
Manufacturer
Micronas Semiconductor
Datasheet
SDA 55xx
12
2. Functional Description
2.1. Clock System
2.1.1. General Function
The on-chip clock generator provides the TVTpro with
its basic clock signal. The oscillator runs with an exter-
nal crystal and the appropriate internal oscillator cir-
cuitry (see Fig. on page 174).
For applications with lower timing accuracy require-
ments (and if the RTC is not used) an external ceramic
resonator can be used. The usage of a ceramic reso-
nator is not recommended for Teletext applications as
depending on the absolute tolerance of the ceramic
resonator the data slicer may not work correctly. Addi-
tional this might also require that display timing param-
eters and the baud rate prescaler have to be adapted.
In timing critical applications the horizontal frequency
of the incoming CVBS signal can be used to measure
the actual timing deviation and to re-program the clock
PLL.
The 6 MHz clock signal is used to generate the internal
300 MHz display reference clock by means of an on-
chip phase locked loop (PLL). The PLL can be
bypassed to reduce the power consumption. If an
immediate wake up from power down is not required
the PLL can also be switched off in this mode.
From the output frequency of the main clock PLL two
clock systems are derived.
Fig. 2–1: Clock System of TVText Pro
XTPADIN
XTPADOUT
Hin
PF
OSC
OSCCLK
6 MHz
PLL
66.67
or
6MHz
MHz
200
300 MHz
: n
: 2
SD
33.33
or
3MHz
33.33
8.33
MHz
DTO
or
CLK_src
Sept. 10, 2004; 6251-556-3DS
33.33 MHz
f
or 8.33 or
sys
3MHz or
ext.clk
CLKE
f
(10 .. 32MHz)
PIX
uC
uC-Periph.
Ports
Sync
ADC
Slicer
CLUTs
DG
2.1.2. System Clock
The 33.33 MHz system clock (f
microcontroller core, all microcontroller related periph-
erals, the sync timing logic, the A/D converters, the
slicer, the display generator and the color lookup
tables CLUT.
It is possible to use 8.33 MHz (1/4 of 33.33 MHz) for
the system clock domain (slow down mode). Setting
SFR-bit PLLS = 1 the user is able to send the PLL into
a power save mode.
Note: Before the PLL is switched to power save mode
To switch back to full frequency operation, the software
has to end the PLL power save mode (SFR-bit
PLLS = 0), reset the PLL for 10 µs (3 machine cycles,
SFR bit PLL_res = ‘1’, then ‘0’ again), wait for 150 µs
(38 machine cycles) and switch back to the PLL clock
(SFR-bit SCR_src = 0).
If the power down mode is activated, PLL and oscilla-
tor are send to sleep mode (SFR bit PDS = 1). Further-
more, there are additional possibilities to disable the
clocks for the peripherals - See Section 2.3.17. on
page 44.
DAC
Display-FIFO
(PLLS = 1), the software has to switch the clock
source from 200 MHz PLL clock to the 3 MHz
oscillator clock (SFR bit CLK_src = 1). In this
mode the slicer, acquisition, DAC and display
generator are switched off.
CPU
) is provided to the
DATA SHEET
Micronas

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