SDA5523 Micronas Semiconductor, SDA5523 Datasheet - Page 130

• Manufacturer Part Number: SDA5523
• Description: SDA55xx TVText Pro
• Manufacturer: Micronas Semiconductor

SDA 55xx
Table 3–4: SFR register description, continued
130
Name
STRVBI
ACQON
Reserved
ACQ_STA
VBIADR[3:0]
PCLK1
PF[10:8]
PCLK0
PF[7:0]
SCR1
Reserved
RGB_G[1:0]
Sub
hD9
hD9[7]
hD9[6]
hD9[5]
hD9[3:0]
hDA
hDA[3:0]
hDB
hDB[7:0]
hE1
hE1[7]
hE1[6:5]
Dir
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
h00
0
0
0
0
h01
1
h48
72
h00
Sept. 10, 2004; 6251-556-3DS
Range
0..1
0..1
0..1
0..31
0..15
0..255
DSYNC
Function
Configuration ACQ & Slicer
Enable Acquisition:
0: The ACQ interface does not access memory (immediately inactive).
1: The ACQ interface is active and writes data to memory (switching
on is synchronous to V).
Config ACQ & Slicer
First Framing code after vertical sync:
0: No framing code after vertical sync has been detected.
1: Framing code after vertical sync has been detected.
The bit is set by hardware and cleared by software.
Defines the 5 MSBs of the start address of the VBI buffer (the LSBs
are fixed to 0x000). The VBI buffer location can be aligned to any 1
kByte memory segment.
DTO Pixel Frequency Factor 1
Pixel Frequency factor (LSBs)
This register defines the relation between the output pixel frequency
and the frequency of the crystal. The pixel frequency does not depend
on the line frequency. It can be calculated by the following formula:
The pixel frequency can be adjusted in steps of 36.6 kHz.
After power-on this register is set to 328d. So, the default pixel
frequency is set to 12.97 MHz.
Attention: Register values greater then 983d generate pixel
frequencies which are outside of the specified boundaries.
DTO Pixel Frequency Factor 0
Pixel Frequency factor (LSBs)
This register defines the relation between the output pixel frequency
and the frequency of the crystal. The pixel frequency does not depend
on the line frequency. It can be calculated by the following formula:
The pixel frequency can be adjusted in steps of 36.6 kHz.
After power-on this register is set to 328d. So, the default pixel
frequency is set to 12.97 MHz.
Attention: Register values greater then 983d generate pixel
frequencies which are outside of the specified boundaries.
DSync Control 1
Reserved for internal use. Must be set to 1 (see Section 2.14. on
page 109).
Used for DAC setup purpose (see Section 2.14. on page 109)
Fpixel = PF * 324 MHz / 8192
Fpixel = PF * 324 MHz / 8192
DATA SHEET
Micronas